(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to create a self-aligned contact structure, where one of the components of the self-aligned contact structure is a metal silicide layer.
(2) Description of Prior Art
Major objectives of the semiconductor industry have been to increase chip performance while still maintaining, or even decreasing the processing cost for these same chips. The ability to create semiconductor devices, with sub-micron features, or micro-miniaturization, has allowed these objectives to be partially realized. Smaller device features result in a reduction in performance degrading capacitances and resistances, thus allowing performance increases to be achieved. In addition, smaller, or sub-micron features, allow smaller chips to be fabricated, however still possessing device densities achieved with larger chips, thus resulting in a greater number of chips to be realized from a specific size substrate, and thus reducing the processing cost for a specific chip.
Micro-miniaturization has been accomplished via enhancements in specific semiconductor fabrication disciplines, such as photolithography and dry etching. The use of more sophisticated exposure cameras, and the use of more sensitive photoresist materials, have allowed sub-micron features to be routinely achieved in photoresist layers. In addition the use of advanced dry etching tools, and processes, have resulted in the successful transfer of the sub-micron images in photoresist layers, to underlying materials, used for the creation of semiconductor devices. However in addition to contributions offered by the advances in semiconductor fabrication disciplines, structural enhancement, such as the use of self-aligned contacts, (SAC), have also been a major contributor to the quest for smaller, higher performing semiconductor chips. The SAC concept entails an opening to a source/drain region, located between word line, or gate structures, of metal oxide semiconductor field effect transistors, (MOSFET), with the SAC opening larger, in width, than the space between word line structures. The opening therefore includes not only the entire width of the source/drain region, but also includes exposure of a portion of the top surface of insulator capped, polycide gate structures. Prior to the use of the SAC technology, designs had to provide more area for source/drain regions, to insure that contact holes would fully land on these regions. That limitation resulting in larger devices, thus higher processing costs.
Metal structures, to source/drain regions, exposed in the SAC opening, described as SAC structures, are usually formed using polysilicon, or metal silicide--polysilicon, (polycide), layers. These structures contact the source/drain region, between polycide gate structures, and overlap the top surface of the insulator capped, polycide gate structures. Prior art, such as Jeng, in U.S. Pat No. 5,706,164, have described SAC structures, comprised of metal silicide on polysilicon, where the metal silicide is a tungsten silicide layer, obtained via a chemical vapor deposition procedure using tungsten hexafluoride and silane as reactants, with the polycide SAC structure, interfacing a polysilicon landing plug, with the polysilicon landing pad contacting the source/drain region. This invention will describe a polycide SAC structure that directly contact the source/drain region, without the use of a polysilicon landing plug, thus demanding excellent step coverage characteristics, needed to traverse the severe topology of the SAC opening. Therefore to improve the step coverage of the polycide SAC structure, dichlorosilane is used in place of silane, along with tungsten hexafluoride, to provide the reactants needed for polycide deposition. The use of dichlorosilane as a reactant, increases the step coverage of the polycide structure in the SAC opening, however necessitates the use of a two step thermal anneal procedure, applied at specific stages of polycide formation, to improve the quality of the dichlorosilane deposited, polycide material.